1. Field of Invention
The present invention relates to a liquid crystal display (LCD) panel, and particularly to a transistor array substrate applied to an LCD panel.
2. Related Art
In a fabrication process for an existing thin film transistor LCD (TFT-LCD), a transistor array substrate is tested after completed, especially for a pixel array of the transistor array substrate, to determine whether the transistor array substrate works normally.
The current transistor array substrate is generally tested by a plurality of shorting bars. FIG. 1 is a schematic top view of a conventional transistor array substrate. Referring to FIG. 1, The conventional transistor array substrate 100 includes a substrate 110, a plurality of pixel arrays 120, a plurality of shorting bars 130, and a plurality of pads 140, in which the pixel arrays 120, the shorting bars 130, and the pads 140 are all disposed on the substrate 110.
Specifically, the substrate 110 has a plurality of panel regions 112 and a peripheral circuit region 114 surrounding the panel regions 112. The pixel arrays 120 are respectively disposed in the panel regions 112, and the shorting bars 130 and the pads 140 are all disposed in the peripheral circuit region 114.
The pixel arrays 120 are generally electrically connected to the shorting bars 130 through a plurality of wires (not shown) in the panel regions 112, and the shorting bars 130 are connected to the pads 140. Therefore, the pixel arrays 120 are electrically connected to the pads 140 through the shorting bars 130, so that a testing machine can test the pixel arrays 120 through the pads 140. In addition, after testing, the substrate 110 is cut, thereby separating the panel regions 112 from the peripheral circuit region 114, and the normally working pixel array 120 combines with a color filter substrate. Thus, a plurality of LCD panels is completed.
It should be noted that about the disposition of the shorting bars 130, most of the shorting bars 130 are densely distributed in a region Z1 between two adjacent panel regions 112 as shown in FIG. 1, and thus a distance D1 between the two adjacent panel regions 112 is hard to be shortened, so that the utility rate of the substrate 110 is difficult to be increased.